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Indian Institute of Science

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Faculty - Navakanta Bhat Faculty List  

Navakanta Bhat
Professor

Room No. - SF 05

Ph: +91 80 2293 3312
Fax: +91 80 2360 6475
E-mail:
navakant@ece.iisc.ernet.in
navakant@gmail.com

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Group webpage:
http://sindhu.ece.iisc.ernet.in/nano/

Associated Departments:
Department of Electrical Communication Engineering (Associate faculty)

Research Areas:

  • Nanoelectronics devices
  • Sensors
  • Circuits

 
Education:
  • Ph.D. EE, 1996, Stanford University, Stanford, CA, USA.
  • M.Tech. Microelectronics, 1992, Indian Institute of Technology, Bombay, India
  • B.E. Electronics & Communication, 1989, SJCE University of Mysore, India
Experience:
  • Professor, Dec. 2010 - Current
  • Associate Professor, Jan. 2005 – Dec. 2010
  • Assistant Professor, Oct. 1999 – Jan 2005
    Indian Institute of Science, Bangalore, India.
  • Device Engineer, Jan. 1997-July 1999,
    Advanced Products R&D Lab, Motorola, Austin, TX USA
 

Research Areas:

  • Nanoelectronics devices - Physics, Technology, Design and Modeling of Silicon and Post Silicon Nano Devices

We address various issues in scalability of Silicon CMOS technology.  One particular emphasis is to develop high-k rare-earth metal oxides as gate dielectrics. We have been able to demonstrate sub-1nm EOT for Er2O3 and Gd2O3. We are also exploring TiO2 and other dielectrics for future DRAM integration. For post silicon materials and device options, we focus on Germanium, III-V and Graphene transistors.  This includes modelling, simulation and experimental work to develop the appropriate device structure, gate dielectric, junctions etc. Some recent highlights include ideal-schottky contact development on Germanium, a novel transistor structure – HFinFET – for III-V, demonstration of very high On to Off current ratio on Graphene transistors.

  • Sensors - Inertial Sensors, Gas Sensors, Bio Sensors

We focus on developing complete sensor platform, integrating transducers and signal conditioning  electronics. This includes high resolution Gyroscope using sub-threshold GyroFET, acoustic sensor, gas sensors platform for environmental pollution monitoring, HbA1c sensor and Intra Cranial Pressure sensors. We also develop sensor arrays, by post processing CMOS integrated circuits.

  • Circuits - Variability Aware Circuit Design, Sensor Interface Circuits

Process variability in Nano CMOS technology has significant impact on circuit and system performance. We focus on modelling the process variability, Process Compact Models, for integration in the design flow. We have developed circuit techniques to do post-fabrication correction for variability and applied it to Memory and Dynamic logic circuits. We have also developed a high resolution capacitance sensing ASIC and low power, high dynamic range resistance sensing ASIC for sensor interface.

 

Selected Publications:

  • Kausik Majumdar, Kota V. R. M. Murali, N. Bhat, and Yu-Ming Lin “External Bias Dependent Direct To Indirect Band Gap Transition in Graphene Nanoribbon”  Nano Letters , 2010
  • Kausik Majumdar, N. Bhat, Prashant Majhi, and Raj Jammy, “Effects of Parasitics and Interface Traps on Ballistic Nanowire FET in the Ultimate Quantum Capacitance Limit”, IEEE Transactions on Electron Devices, 2010
  • K. Majumdar, N. Bhat, P. Mhaji, R. Jammy, “HFinFET: A Scalable, High Performance, Low Leakage Hybrid N-Channel FET,” IEEE Transactions on Nanotechnology, May 2010
  • V. T. Arun, K N Bhat, N. Bhat, M.S. Hegde, “Fermi level de-pinning at the germanium schottky interface through sulfur passivation”, Applied Physics Letters, April 2010
  • Kausik Majumdar, Kota V.R.M.Murali, N. Bhat and Yu-Ming Lin, “Intrinsic limits of subthreshold slope in biased bilayer graphene transistor”, Applied Physics Letters, Vol.96, 123504, doi:10.1063/1.3364142, 2010
  • Balaji Jayaraman, N. Bhat and Rudra Pratap, "Thermal characterization of microheaters from the dynamic response," Journal of Micromechanics and Micoengineering, Vol. 19, 085006 (11pp), 2009
  • R. G. D. Jeyasingh, N. Bhat, B. Amrutur, “Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique,” IEEE Transactions on VLSI Systems, November 2009 
  • C.Venkatesh and N. Bhat, "Reliability Analysis of Torsional MEMS Varactor", IEEE Transactions on Device and Materials Reliability, pp 129-134, March 2008
  • B.P. Harish, N. Bhat, and Mahesh B. Patil, “On A Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 26(3):pp. 606-614, 2007
  • M.P. Singh, C.S. Thakur, K. Shalini, N. Bhat, and S.A. Shivashankar, “Structural and Electrical Characterization of Erbium Oxide Films Grown on Si(100) by Low-pressure Metalorganic Chemical Vapour Deposition”, Applied Physics Letters, October 2003
 

Publications List:

  1. Kausik Majumdar, Kota V. R. M. Murali, N. Bhat, and Yu-Ming Lin “External Bias Dependent Direct To Indirect Band Gap Transition in Graphene Nanoribbon”  Nanoletters (Available online)
  2. Kausik Majumdar, N. Bhat, Prashant Majhi, and Raj Jammy, “Effects of Parasitics and Interface Traps on Ballistic Nanowire FET in the Ultimate Quantum Capacitance Limit”, IEEE Transactions on Electron Devices (Available online)
  3. K. Majumdar, N. Bhat, P. Mhaji, R. Jammy, “HFinFET: A Scalable, High Performance, Low Leakage Hybrid N-Channel FET,” IEEE Transactions on Nanotechnology, May 2010
  4. V. T. Arun, K N Bhat, N. Bhat, M.S. Hegde, “Fermi level de-pinning at the germanium schottky interface through sulfur passivation”, Applied Physics Letters, April 2010
  5. Kausik Majumdar, Kota V.R.M.Murali, N. Bhat and Yu-Ming Lin, “Intrinsic limits of subthreshold slope in biased bilayer graphene transistor”, Applied Physics Letters, Vol.96, 123504, doi:10.1063/1.3364142, 2010
  6. Jayaraman, B., Singh, V. R., Asundi, A., Bhat, N. and Hegde, G. M. ‘‘Thermomechanical characterization of surface-micromachined microheaters using in-line digital holography,” Measurement Science & Technology, IOP, Vol. 21, 015301 (10pp), 2010
  7. R. G. D. Jeyasingh, N. Bhat, B. Amrutur, “Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique,” IEEE Transactions on VLSI Systems, November 2009 (Available online)
  8. Ajayan K.R., N. Bhat, “Linear transconductor with flipped voltage follower in 130 nm CMOS,”  Analog Integr Circ Signal Processing, Kluwer, 13 October 2009
  9. Balaji Jayaraman, N. Bhat and Rudra Pratap, "Thermal characterization of microheaters from the dynamic response," Journal of Micromechanics and Micoengineering, Vol. 19, 085006 (11pp), 2009
  10. S. Bagga, N. Bhat and S.Mohan, ‘‘LPG Gas-Sensing System With SnO2 Thin-Film Transducer and 0.7-mu m CMOS Signal Conditioning ASIC”, IEEE Transactions on Instrumentation and Measurement 58: 3653-3658, 2009
  11. Balaji Jayaraman, N. Bhat and Rudra Pratap, "Thermal analysis of microheaters using mechanical dynamic response," International Journal of Micro and Nano systems, 1(1), pp. 15 – 20, 2009
  12. B. Jayaraman and N. Bhat, “Performance analysis of subthreshold cascode current mirror in 130nm CMOS technology,” J. Low Power Electronics, Vol. 5, No. 4, pp. 484 – 496,  Dec. 2009
  13. Santosh Hegde, Thejas, N. Bhat, “Universal Capacitance Sensor”, International J. of Micro and Nano Systems,” 1(1),2009,pp.21-27, 2009
  14. B. P. Harish, N. Bhat, and Mahesh B. Patil, “Hybrid-CV Modeling for Estimating the Variability in Dynamic Power” J. Low Power Electronics ASP 4, 263–274 December (2008)
  15. K. Majumdar, N.Bhat, “Bandstructure Effects in Ultra-Thin-Body Double-Gate Field Effect Transistor: A Fullband Analysis” Journal of Applied Physics, Volume 103, Issue 11, pp. 114503-114503-9 (2008)
  16. R. Srinivasan and N. Bhat, “Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance” J. Low Power Electronics, ASP 4, 240-246 August (2008)
  17. C. Venkatesh and N. Bhat, "Reliability Analysis of Torsional MEMS Varactor", IEEE Transactions on Device and Materials Reliability, pp 129-134, March 2008
  18. M.P. Singh, K. Shalini, S.A. Shivashankar, G.C. Deepak, N. Bhat, T. Shripathi, “Microstructure, crystallinity, and properties of low-pressure MOCVD-grown europium oxide films”, Materials Chemistry and Physics, Elsevier, 110 : 337-343, 2008
  19. B.P. Harish, N. Bhat, and Mahesh B. Patil, “On A Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 26(3):pp. 606-614, 2007
  20. N. Bhat, “Nanoelectronics Era : Novel Device Technologies Enabling Systems on Chip”, J. Indian Institute of Science, vol. 87: 1, Jan-Mar 2007, pp. 61-74
  21. G. Krishnan, C. U. Kshirasagar, G.K.Ananthasuresh, N. Bhat, “Micromachined High-Resolution Accelerometers”, J. Indian Institute of Science, vol. 87: 3, Jul-Sept 2007
  22. B.P. Harish, N. Bhat, and Mahesh B. Patil, “Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes”, Solid State Electronics,  Vol. 50, pp 1252-1260, (2006)
  23. M. P. Singh, K. Shalini, and S. A. Shivashankar, G.C.Deepak and N. Bhat, “Structural and electrical properties of low pressure metalorganic chemical vapor deposition grown Eu2O3 films on Si(100)”, Applied Physics Letters 89, 201901, 2006
  24. R. Sreenivasan and N. Bhat, “Effect of Gate-Drain/Source Overlap on the noise in 90nm NMOSFETs” Journal of Applied Physic, 2006
  25. R Srinivasan and N. Bhat, “Scaling Characteristics of fNQS and ft in NMOSFETs with Uniform and Non-uniform Channel Doping”, International Journal of Electronics, Taylor and Francis Group, Vol 92, No 12, Dec 2005
  26. R Srinivasan and N.Bhat, “Scaling Characteristics of fNQS and ft in NMOSFETs with and without Supply Voltage Scaling”, J. of Indian Institute of Science, Vol 85, Aug 2005
  27. A. Gupta and N. Bhat, “On the Performance Analysis of a Class of Neuron Circuits”, Analog Integrated Circuits and Signal Processing, Kluwer 44 (3), pp.  293-302, September 2005
  28. C. Venkatesh, S. Pati, N. Bhat and R. Pratap, “A Torsional MEMS Varactor with Wide Dynamic Range and Low Actuation Voltage”, Sensors and Actuators A Physical, June 2005
  29. H.C. Srinivasaiah and N. Bhat, “Characterization of Sub-100nm CMOS Process Using Screening Experiment Technique”, Solid State ElectronicsVol. 49, pp 431-436, (2005)
  30. A. Gupta and N. Bhat, “Asymmetric Cross-Coupled Differential Pair Configuration to Realize Neuron Activation Function and its Derivative”, IEEE Transactions on Circuits and Systems Part II: Express Briefs, Vol. 52, No. 1, pp. 10-13, January 2005
  31. M.P. Singh, C.S. Thakur, K. Shalini, S. Banerjee, N. Bhat, and S.A. Shivashankar, “Structural, Optical, and Electrical Characterization of Gadolinium Oxide Films Deposited by Low-pressure Metalorganic Chemical Vapour Deposition”, Journal of Applied Physic, Vol 96, No. 10, pp. 5631-5637, 15 November 2004 
  32. A. Gupta and N. Bhat, Back-Gate Effect to Generate Derivative of Neuron Activation Function”, Analog Integrated Circuits and Signal Processing, Kluwer 41 (1), pp.  89-92, October 2004
  33. R. Singh and N. Bhat, “An Offset Compensation Technique for Latch Type Sense Amplifier in High Speed Low Power SRAMs”, IEEE Transactions on VLSI Systems, June 2004, pp. 652-657
  34. K. Maitra and N. Bhat, “Impact of Gate to Source/Drain Overlap Length on 80 nm CMOS Circuit Performance”, IEEE Transactions on Electron Devices, March 2004 pp.409-414
  35. N. Bhat, “MEMS for RF Applications”, IETE Technical Review, vol. 21, no. 2, March-April 2004
  36. N. Bhat and C.S.Thakur, “Analog CMOS Performance Degradation due to Edge Direct Tunneling (EDT) Current in sub-100nm Technology” invited paper for Journal of Semiconductor Technology and Science special issue on Device Reliability, September 2003
  37. M.P. Singh, C.S. Thakur, K. Shalini, N. Bhat, and S.A. Shivashankar, “Structural and Electrical Characterization of Erbium Oxide Films Grown on Si(100) by Low-pressure Metalorganic Chemical Vapour Deposition”, Applied Physics Letters, October 2003
  38. H C Srinivasaiah and N. Bhat, Monte Carlo Analysis of the Implant Dose Sensitivity in 0.1 m NMOSFET”, Solid-State Electronics, 47/8 pp. 1379-1383, August 2003
  39. H C Srinivasaiah  and N. Bhat, “Mixed Mode Simulation Approach to Characterize the Circuit Delay Sensitivity to Implant Dose Variations”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 22 , no. 6, pp. 742-747, June 2003
  40. P.K.Saxena  and N.Bhat, “Process technique for SEU reliability improvement of deep sub-micron SRAM cell”, Solid-State Electronics, Vol. 47, 4, April 2003, pp. 661-664
  41. P.K.Saxena  and N.Bhat, SEU Reliability Improvement Due to Source-Side Charge Collection in the Deep-Submicron SRAM Cell”, IEEE Transactions on Device and Material Reliability, pp.14-17 March 2003
  42. K. Maitra and N. Bhat, “Polyreoxidation process step for suppressing edge direct tunneling through ultrathin gate oxides in NMOSFETs”, Solid-State Electronics, Vol. 47, 1, January 2003, p. 15-17
  43. K. Maitra and N. Bhat, “Analytical approach to integrate the different components of direct tunneling current through ultrathin gate oxides in n-channel metal oxide semiconductor field-effect transistors”, Journal of Applied Physics, Vol 93, No. 2, pp. 1064-1068, 15 January 2003
  44. N. Bhat, A. Wang and K.C. Saraswat, “Rapid thermal anneal of gate oxides for low thermal budget TFTs,” IEEE Transactions on Electron Devices, p.63, January 1999
  45. N. Bhat,  and K.C.Saraswat, “Characterization of border trap generation in rapid thermally annealed oxides deposited using silane chemistry”, Journal of Applied Physics, p. 2722, September 1998
  46. N. Bhat, M. Cao and K.C. Saraswat, “Bias temperature instability in hydrogenated thin-film transistors,” IEEE Transactions on Electron Devices, p.1102, July 1997
  47. N. Bhat, P.P. Apte and K.C. Saraswat, “Charge trap generation in LPCVD oxides under high field stressing,” IEEE Transactions on Electron Devices, p.554,  April 1996
  48. N. Bhat, and J.Vasi, “Interface-state generation under radiation and high field stressing in reoxidized  nitrided oxide MOS capacitors,” IEEE Transactions on Nuclear Science, p.2230, Dec. 1992
 

Selected conferences & seminars:

  • Kausik Majumdar, Kota V. R. M. Murali, N. Bhat, Fengnian Xia and Yu-Ming Lin, “High On-Off Ratio Bilayer Graphene Complementary Field Effect Transistors”, IEDM 2010
  • B.P. Harish, N. Bhat, and Mahesh B. Patil, “Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits”, Invited talk at IEEE International Symposium on Circuits and Systems, VOLS 1-5 Pages: 2309-2312, 2009
  • AdityaSankar Medury, N. Bhat and K.N.Bhat "Modeling theThreshold Voltage of Ultra-Thin-Body(UTB) Long Channel Symmetric Double-Gate (DG) MOSFETs" International Semiconductor Device Research Symposium(ISDRS), Dec 2009
  • N. Bhat, B. Jayaraman, R. Pratap, S. Bagga, S. Mohan, “Integrated CMOS Gas Sensor System”, Invited talk at the International conference on Electron Devices and Semiconductor Technology (IEDST), 2009
  • C. Malhi, R. Pratap, N. Bhat, "High Sensitivity FET Integrated MEMS Deflection Sensor", IEEE Sensors 2009
 

Patents:

  1. N. Bhat, K N Bhat, V T Arun, “Modification of Fermi-level pinning behavior at the Germanium surface through sulfur passivation treatment” , Indian Patent filed
  2. B. Amrutur, N. Bhat,  “Large  Flexible Surfaces with an Embedded, Dense, Sensing and Actuation  Network for Bio-Electronic applications” Indian and US Patent filed
  3. B. Amrutur, N. Bhat, S. Dwivedi, “Adaptive Digital Baseband Receiver” , Indian Patent Filed, 2596/CHE/2009 , October 2009
  4. N. Bhat, Balaji Jayaraman, S.A.Shivashankar, Rudra Pratap, “A sub-threshold Cap-FETsensor for sensing analyte, a method and system thereof”    Indian Patent Application Number: 906/CHE/2007, International PCT Application Number: PCT/IN2008/000385
  5. N. Bhat, Thejas, Rudra Pratap, “A sub-threshold Forced plate-FET sensor for sensing inertial displacements, a method and system thereof”, Indian Patent Application Number: 907/CHE/2007
    International PCT Application Number: PCT/IN2008/000386
  6. N. Bhat, C. Malhi, Rudra Pratap, “A sub-threshold Elastic deflection-FET sensor for sensing pressure/force, a method and system thereof”, Indian Patent Application Number: 929/CHE/2007, International  PCT Application Number: PCT/IN2008/000387
  7. N. Bhat and Rakesh Gnana David J., “An adaptive keeper circuit to control domino logic dynamic circuits using rate sensing technique”, Patent filed,  International application PCT/IN2007/000259, Indian Patent No.01130/CHE/2007
  8. N. Bhat and S. Mukherjee, “Yield and Speed Enhancement of Semiconductor Integrated Circuits using Post Fabrication Transistor Mismatch Compensation Circuitry”, US patent #6934200
  9. P. Tsui, H. Tseng, N. Bhat and P. Chen, “Method for making a dual thickness gate oxide layer using a nitride/oxide composite region”, US patent #5960289
  10. P. Chen, N. Bhat, D. Pham, P. Tsui, “Process for forming semiconductor device with thick and thin films,” US Patent #6,261,978
 

Gallery:

Fig. 1 Direct to indirect bandgap transition in Graphene Nanoribbon (Research area: Nanoelectronic Devices)

 
Fig. 2 Fermi level depinning at the germanium Schottky interface through sulfur passivation (Research area: Nanoelectronic Devices)
 

Fig. 3 HFinFET: A hybrid of HEMT and FinFET (Research area: Nanoelectronic Devices)

 

Fig. 4 Thermal characterization of microheaters from the dynamic response (Research area: Sensors)

 

Fig. 5 Torsional MEMS varactor (Research area: Sensors)

 

Fig. 6 Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique (Research area: Circuits)

 

 
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